`timescale 1ns/100ps
module fenpin_test;
  reg clk;
  reg rst;
  wire cout;
  wire [5:0] m;
  wire [5:0] n;
  wire cout1,cout2;
 mod_19 u1(rst,clk,cout,cout1,cout2,m,n);
  always #5 clk=~clk;
  initial
  begin 
    clk=0;
    rst=0;
    #10 rst=1;
    #2000 $stop;
  end
  initial 
  $monitor($time, , ,"clk=%b rst=%d cout1=%b cout2=%b cout=%b m=%d n=%d",clk,rst,cout1,cout2,cout,m,n);
endmodule